1. Field of the Invention
The present invention relates to an apparatus and method for deposition and planarization of a material, such as a metal, on a substrate.
2. Background of the Related Art
Sub-quarter micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
In the fabrication of integrated circuits and other electronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited on or removed from a surface of a substrate. Thin layers of conducting, semiconducting, and dielectric materials may be deposited by a number of deposition techniques. Common deposition techniques in modem processing include physical vapor deposition (PVD), also known as sputtering, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and now electrochemical plating (ECP).
As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials. Planarization is also useful in forming features on a substrate by removing excess deposited material used to fill the features and to provide an even surface for subsequent levels of metallization and processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. CMP utilizes a chemical composition, typically a slurry or other fluid medium, for selective removal of material from substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing pad in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing pad. The pad is moved relative to the substrate by an external driving force. The CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing pad while dispersing a polishing composition, or slurry, to effect chemical activity and/or mechanical activity and consequential removal of material from the surface of the substrate.
Copper is becoming a metal of choice in ULSI to form the interconnects that provide the conductive pathway in integrated circuits and other electronic devices. Copper is a material having advantageous properties such as lower resistance and better electromigration performance compared to traditional materials such as aluminum. Copper can be deposited by various techniques such as PVD, CVD and electroplating. Electroplating (ECP) is seen as a low cost and effective deposition technique with promise. ECP is performed by introducing a substrate into a plating bath and applying a current to the substrate. The copper ions plate out of solution and deposit onto the substrate.
However, copper is difficult to pattern and etch. Accordingly, copper features are formed using damascene or dual damascene processes. In damascene processes, a feature is defined in a dielectric material and subsequently filled with copper. A barrier layer is deposited conformally on the surfaces of the features formed in the dielectric layer prior to deposition of the copper. Copper is then deposited over the barrier layer and the surrounding field. The copper deposited on the field is removed by CMP processes to leave the copper filled feature formed in the dielectric material. Both abrasive and abrasive free CMP processes are available and others are being developed to remove copper. Abrasives refer to additives in the slurry or formed in a polishing pad which provide mechanical abrasion of a surface being polished. One example of an abrasive is silica particles in a polishing slurry.
FIG. 1 illustrates the step height of deposited materials, such as copper, over various features formed on a substrate surface. For features smaller than 1 μm, the surface of the deposited copper over the feature is higher than on the field; however, for features lager than 1 μm, the field surface is higher. To achieve complete planarization over wide features, it is necessary to deposit a copper thickness ˜1.4-1.6 times that of the intra-level dielectric (ILD) thickness. For typical power lead levels, a 2.0 μm thick copper layer is required. However, the deposition of this thick copper layer will limit the throughout of CMP.
Another problem with CMP of copper is the tendency of copper surfaces to dish as a result of polishing. Dishing can result from copper over-polish used to clear all copper formed on the field across the whole wafer. One area where dishing may occur is in areas where conductive features exceed five (5) microns. This is particularly problematic in some current designs where the conductive features are often greater than about ten (10) microns. To prevent excessive dishing in these surfaces during CMP processing, oxide pillars are typically interposed in these features to reduce the width of the conductive feature exposed to CMP processing.
As a result, there is a need for an apparatus and method for depositing and planarizing a metal layer, such as a copper layer, on a substrate.